Programs

Description

Once RTL code has been written by RTL designers in Verilog or System Verilog or VHDL, the code is functionally verified and simulated. What next? Implementation starts with Synthesis, to Physical Implementation and SignOff before the design is handed off to the foundry for fabrication. Physical Design overing Synthesis, Physical Implementation, STA and other signoff is key in meeting the designs PPA (Power Performance Area). This role involves lots of scripting for methodology, flow and good amount of graphical interpretation with logical, analytical and mathematical aptitude.